If backwards compatibility bothers you, then replace it with “a series of well defined ISAs”
This is exactly what I’m saying, its not well defined architecture. You never know if the next ARM CPU will be compatible or not to any existing variants.
which still does not define the RISC philosophy as a whole
What do you mean? ARM is a RISC CPU. The entire philosophy of RISC is that anyone can implement this RISC system, and no guarantees are made to be compatible with any prior CPU. We have RISC CPUs since the beginning of 80s.
The official Acorn RISC Machine (ARM) project started in October 1983.
RISC literally just means reduced instruction set architecture. Any CPU that has a small amount of instructions (defined somewhat arbitrarilly) is considered to be a RISC CPU as opposed to a CISC (complex instruction set architecture) CPU. The idea behind RISC is to improve performance by reducing bloat, but the tradeoff is that performing more complex tasks takes more instructions to do.
Yes, but they could have compatibility like x86. The difference is that every CPU creator can have different sets, not just a superset. That’s why ARM is not well defined, because its by nature cannot be. There is no definition of what an ARM or RISC CPU has to offer or be compatible to.
ARM is a series of ISAs, which are strict definitions which CPUs must conform to to be considered ARM compatible. RISC has no set or sets of ISAs, and is more of a philosophy.
If one company, like Mediatek or Qualcomm makes an AARCH64 CPU, compiles a binary for a common operating system, like Linux, and wants to run it on the others’ CPU, that is possible because the ISA for AARCH64 is strictly defined.
On the other hand, take two incompatible RISC architectures, say one CPU that uses MIPS and another RISC-V, and try to run binaries compiled for the other architecture, then try to run it. It will not run because they are inherently incompatible, even though they are both a subset of the wider RISC umbrella.
Also depending on which ARM assembly programmer you ask, modern ARM isn’t even really RISC due to its complexity despite the name. That is a whole other unrelated conversation, though.
Every CPU is a definition. Even if there is only one. That’s not the point. I also said already that ARM is an implementation of the RISC idea. What makes ARM not being strictly defined is, that no one has to follow an existing ARM CPU definition. Its like saying that every CPU with a branding is strictly defined, yes obviously they are defined for themselves, otherwise it wouldn’t be possible to build one.
I feel like we’re talking past each other. I’m not saying you are wrong, at least in the sense what you are trying to say.
This is exactly what I’m saying, its not well defined architecture. You never know if the next ARM CPU will be compatible or not to any existing variants.
What do you mean? ARM is a RISC CPU. The entire philosophy of RISC is that anyone can implement this RISC system, and no guarantees are made to be compatible with any prior CPU. We have RISC CPUs since the beginning of 80s.
RISC literally just means reduced instruction set architecture. Any CPU that has a small amount of instructions (defined somewhat arbitrarilly) is considered to be a RISC CPU as opposed to a CISC (complex instruction set architecture) CPU. The idea behind RISC is to improve performance by reducing bloat, but the tradeoff is that performing more complex tasks takes more instructions to do.
Yes, but they could have compatibility like x86. The difference is that every CPU creator can have different sets, not just a superset. That’s why ARM is not well defined, because its by nature cannot be. There is no definition of what an ARM or RISC CPU has to offer or be compatible to.
ARM is a series of ISAs, which are strict definitions which CPUs must conform to to be considered ARM compatible. RISC has no set or sets of ISAs, and is more of a philosophy.
If one company, like Mediatek or Qualcomm makes an AARCH64 CPU, compiles a binary for a common operating system, like Linux, and wants to run it on the others’ CPU, that is possible because the ISA for AARCH64 is strictly defined.
On the other hand, take two incompatible RISC architectures, say one CPU that uses MIPS and another RISC-V, and try to run binaries compiled for the other architecture, then try to run it. It will not run because they are inherently incompatible, even though they are both a subset of the wider RISC umbrella.
Also depending on which ARM assembly programmer you ask, modern ARM isn’t even really RISC due to its complexity despite the name. That is a whole other unrelated conversation, though.
Every CPU is a definition. Even if there is only one. That’s not the point. I also said already that ARM is an implementation of the RISC idea. What makes ARM not being strictly defined is, that no one has to follow an existing ARM CPU definition. Its like saying that every CPU with a branding is strictly defined, yes obviously they are defined for themselves, otherwise it wouldn’t be possible to build one.
I feel like we’re talking past each other. I’m not saying you are wrong, at least in the sense what you are trying to say.